Intel's PowerVia to Boost PC Chip Speeds in 2024

Dennis Faas's picture

In an attempt to regain its chip making advantage, Intel is set to introduce PowerVia, a new technology that could enhance the speed of its 2024 PC chips. While Intel faces tough competition from leading companies like Taiwan Semiconductor Manufacturing Co. (TSMC) and Samsung, the introduction of PowerVia could help Intel bridge the gap and even entice competitors to utilize its manufacturing services.

Arrow Lake Processors to Receive Significant Speed Boost

Intel's forthcoming Arrow Lake processor, slated for release in 2024, will benefit from a substantial speed boost thanks to PowerVia. In recent tests, Intel demonstrated that this new power delivery technique provided a 6% increase in speed for test chips. Furthermore, Arrow Lake will introduce another feature called RibbonFET, which is expected to offer additional advantages. (Source:

Intel has faced challenges in reclaiming its former chip making dominance, which was overtaken by TSMC and Samsung. These are Intel's main competitors, producing chips for major players like Apple, AMD, Nvidia, and Qualcomm.

However, PowerVia's arrival in 2024, alongside the Intel 20A manufacturing process (A = Angstroms, which replaces Nanonmeters [nm] die size), followed by improvements with the 18A process in 2025, could enable Intel to better match rival chips in terms of circuitry integration and energy efficiency. This would allow for extended battery life and even fanless designs, as seen in Apple's MacBook laptops.

PowerVia uses 'Backside Power Delivery'

Chips rely on tiny transistors to process data and perform calculations, necessitating a continuous supply of electrical power. Traditionally, this power is delivered through intricate 3D wiring networks that also carry instruction signals. However, with Arrow Lake, Intel plans to separate power delivery from communication links by implementing a backside power delivery network, known as PowerVia.

Intel's PowerVia technology represents a major change in on-chip interconnects, offering improvements in power, performance, area, and cost. By relocating power delivery to the opposite face of the chip, Intel aims to optimize the design and enhance overall transistor functionality.

However, according to Tirias Research analyst Kevin Krewell, PowerVia appears to be a promising incremental step for Intel but may is likely not provide a long-term advantage.

He predicts that other competitors will eventually adopt similar technologies. Moreover, Intel's ambitions could result in some of its current competitors becoming its customers, benefiting from the PowerVia technology. This scenario aligns with Intel's vision of potentially manufacturing the Apple processor that would power future iPhones.

PowerVia to Pave the Way Forward

Intel has incorporated PowerVia into test chips manufactured using its current Intel 4 process, which is also employed in the production of elements for the Meteor Lake processor. PowerVia's success paves the way for its integration into the future Intel 20A and 18A processes.

The Intel 4 process currently uses 7nm die size, but is moving to 4nm later this year. (Source:

Intel's recovery efforts have been fueled by the need to keep up with Moore's Law and stay at the forefront of transistor miniaturization. While other companies like Samsung and TSMC are also developing backside power delivery technologies, Intel's PowerVia technology holds the potential to provide a competitive advantage.

What Impact Will Intel's New Manufacturing Die Size Have?

As discussed earlier, Intel's manufacturing process is moving toward Angstroms. Previously measured in Nanometers (nm), Angstroms (A) are units of measurement used in the field of semiconductor technology to quantify the size of features on a microchip. However, they differ in terms of scale and the specific aspects they represent.

To put things into perspective, in 1990, the PowerPC chip was built on a 1,000 nm die size. In 2023, both Intel and AMD utilize 4nm dies. (Source:


Nanometer is a unit of length equal to one billionth of a meter (10^-9 meters). In semiconductor manufacturing, the term "nanometer" is commonly used to describe the process technology node, which refers to the size of the smallest feature that can be created on a microchip. For example, a 10nm process technology means that the smallest feature size achievable on the chip is approximately 10nm.

As the semiconductor industry progresses, manufacturers aim to shrink the size of these features to pack more transistors onto a chip, improving performance, power efficiency, and speed. Smaller feature sizes allow for the creation of more intricate and densely packed circuits, enabling faster processing speeds and reduced power consumption.


Angstrom is a unit of length equal to one ten-billionth of a meter (10^-10 meters) or 0.1 nanometers. Angstrom is typically used to measure atomic-scale distances and dimensions. In the context of semiconductors, Angstroms are often used to describe the thickness of certain layers or the distance between individual atoms within a material.

In semiconductor manufacturing, the precise control and manipulation of atomic-scale layers and structures are critical to the performance and reliability of the chips. This includes the thickness of insulating layers, the size of transistor gates, and the spacing between different components. The ability to measure these atomic-scale distances in Angstroms is crucial for ensuring the accuracy and effectiveness of semiconductor fabrication processes.

Impact on Semiconductor Efficiency and Speed

The size of features on a microchip, measured in nanometers, directly influences the efficiency and speed of semiconductor devices. Smaller feature sizes allow for higher transistor density, enabling more transistors to be packed onto a chip. This leads to increased computational power and improved performance. Additionally, smaller features reduce the distance that electrical signals need to travel within the chip, resulting in faster data transfer and reduced latency.

However, as feature sizes approach the atomic scale, new challenges arise. Quantum mechanical effects and physical limitations start to impact the behavior of transistors, causing leakage currents, power consumption issues, and increased manufacturing complexity. Therefore, achieving smaller feature sizes requires advanced manufacturing techniques and materials to mitigate these challenges and maintain semiconductor efficiency and speed.

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